Integrated circuit designers often desire to increase the level of integration or density of elements within an integrated circuit by reducing the size of the individual elements and by reducing the separation distance between neighboring elements. In addition, integrated circuit designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
A relatively common integrated circuit device is a memory device. A memory device may include a memory array having a number of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes one access device, such as a transistor, and one memory storage structure, such as a capacitor. Modern applications for semiconductor devices can utilize vast numbers of DRAM unit cells, arranged in an array of rows and columns. The DRAM cells are electrically accessible through digit lines and word lines arranged along the rows and columns of the array.
DRAM access devices typically comprise a channel region between a pair of source/drain regions, and a gate configured to electrically connect the source/drain regions to one another through the channel region. Access devices that have channel regions that are primarily parallel to a primary surface of a semiconductor substrate are referred to as planar access devices (e.g., planar transistors), and those having channel regions that are generally perpendicular to the primary surface of the substrate are referred to as vertical access devices (e.g., vertical transistors). Planar access devices can be distinguished from vertical access devices based upon the direction of current flow as well as on the general orientation of the channel region. Current flow between the source and drain regions of a vertical access device is primarily substantially orthogonal to a primary surface of the semiconductive substrate or base thereunder, and current flow between source and drain regions of a planar access device is primarily parallel to the primary surface of the semiconductive substrate or base thereunder. There is continuing interest in the development of methodologies by which vertical access devices can be incorporated into integrated circuitry applications due to, among other things, advantages in packing density that can be obtained utilizing vertical access devices relative to planar access devices.
Double-gate vertical access devices have been developed for next-generation 4 F2 DRAM cells (i.e., where “F” represents minimum lithographic feature width). Such vertical double-gate vertical access devices typically include a single, unitary semiconductor pillar (e.g., fin) vertically protruding from an active surface of the semiconductor substrate or base. A conductive material may be deposited over a central portion of the semiconductor pillar and patterned to form a pair of gates, serving as word lines, on opposite sides of the semiconductor pillar. However, difficulties are frequently encountered in producing the vast arrays of double-gate vertical access devices desired for semiconductor DRAM applications while maintaining suitable performance characteristics of the devices. For example, DRAM manufacturers face a tremendous challenge on shrinking the memory cell area as the word line spacing, i.e., the spacing between two adjacent word lines, continues to shrink. The shrinking spacing between two closely arranged word lines leads to undesirable electrical coupling effects for high-speed DRAM applications, and also leads to an increase in pattern noise.
It would, therefore, be desirable to have improved vertical access devices and semiconductor device structures facilitating higher packing densities with minimal electrical coupling effects and pattern noise, as well as methods of forming such vertical access devices and semiconductor device structures.